The present invention relates to integrated circuits and, more particularly, to delay management and compensating for on and off-chip process, voltage, and temperature (PVT) variations in integrated circuits.
Some semiconductor devices are connected to a controller for receiving clock signals for performing operations such as reads, writes, data processing, and the like. Examples of such semiconductor devices include input/output (I/O) drivers, flash memories, universal bus transmitters, voltage regulators, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc. A system-on-chip (SoC) is an integrated circuit (IC) that includes multiple circuits including a controller that provides clock signals to the circuits. The SoC may be connected to multiple external memories for receiving data. The external memories also receive clock signals from the controller. When the controller outputs the clock signals to an external memory, the clock signals pass through multiple logic modules before being received by the external memory, such as a printed circuit board (PCB), a programmable logic array (PLA), and a programmable array logic (PAL), which introduce delays in the clock signals. When the external memory receives the clock signals, it outputs the data requested by the controller. The data is received by the controller by way of the multiple logic modules, thereby adding additional delay in reception of the data. The difference between the time when the controller outputs the clock signals and the time when the external memory outputs the data after receiving the clock signals corresponds to a valid time.
The controller operates at high frequency to fetch a maximum amount of data from the external memory in a given time period. The external memory outputs the data, at every valid clock edge of the data read instruction. At high operating frequencies, external memory, like Flash memory, takes approximately 80% of the clock cycle of a data read instruction to output the valid data, so the controller is left with just the remaining 20% of the clock cycle to capture the data from the external memory—this is called a read data valid window. Due to the long read data path from the external device to the controller, along with the fact that the read data valid window is much smaller than the clock cycle, the controller may not have enough time to capture the valid data, which can result in data loss. Such data loss can be a critical issue especially, for example, if data being fetched is boot data essential for booting the system.
As the number of semiconductor devices and components included in the system is increasing, the size of the boot data required for booting the system also is increasing. The boot data includes a directory of operation codes (opcodes) that initialize the semiconductor devices and the components of the system. The controller must capture the boot data in the available read data valid window. At high frequency, due to the small duration of the read data valid window, the controller may be unable to read the boot data, which can lead to unreliable system boot or even failure to boot at high interface frequencies.
A known technique to solve the problem of not being able to reliably read the boot data at high frequencies is to use delay cells to shift the clock so that the clock edges lie within the valid read data window. Typically, the delay cells include multiple digital circuits such as logic gates and multiplexers, which introduce a delay in the clock signal of the controller receiving the data from the external memory. The delay cells ensure that the controller has sufficient time to receive the data. The delay corresponds to a phase shift in the clock signal.
As is well known, changes in operating conditions such as ambient temperature, operating voltage, and circuit delays caused by process variations (collectively PVT variations) affect the delay introduced by the delay cells. The delay cells have a fixed delay value for each PVT corner. A PVT corner indicates a speed of operation given a supply voltage and an operating temperature of the semiconductor device and/or the external memory. For instance, the PVT corner (fast, 1.1 volts, −25° C.), corresponds to a fast speed of operation at a supply voltage of 1.1 V and an operating temperature of −25° C. of the semiconductor device. Thus, change in the PVT corners of the delay cells leads to a mismatch in the delay introduced in the clock signal and the read data valid window. The mismatch further leads to data loss in read operations. As the delay cells do not introduce different delays when the controller and the external memories are at different PVT corners, the use of the delay cells to shift the clock so that the clock edge of the clock is present in the read data valid window is not effective. Further, the delay cells only attempt to accommodate on-chip PVT variations, but not off-chip PVT variations, which further exacerbates the problem.
Thus, it would be advantageous to have a system that can compensate for both on and off-chip PVT variations.